`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/09/09 12:48:58
// Design Name: 
// Module Name: clock_ctl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module clock_ctl(
    input reset,
    
    input clk_in0,
    input clk_in1,
    input clk_in2,
    input clk_in3,
    output clk_out,
    
    input bus_din_en,
    output [15:0] bus_din_data,
    input bus_dout_en,
    input [15:0] bus_dout_data,
    input [1:0] bus_dout_mask
    );

parameter DEFAULT_CLOCK = 0;

reg [1:0] sel;
wire [1:0] clk_sel1;

BUFGMUX(.O(clk_sel1[0]), .I0(clk_in0), .I1(clk_in1), .S(sel[0]));
BUFGMUX(.O(clk_sel1[1]), .I0(clk_in2), .I1(clk_in3), .S(sel[0]));

BUFGMUX(.O(clk_out), .I0(clk_sel1[0]), .I1(clk_sel1[1]), .S(sel[1]));

assign bus_din_data = {14'b0, sel};

always @(posedge clk_out or posedge reset)
    if (reset)
        sel <= DEFAULT_CLOCK;
    else if (bus_dout_en) begin
            if (bus_dout_mask[0])
                sel <= bus_dout_data[1:0];
    end

endmodule
